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| ltc2446/ltc2447 1 24467fa features descriptio u applicatio s u typical applicatio u flow weight scales pressure direct temperature measurement gas chromatography five selectable differential reference inputs four differential/eight single-ended inputs 4-way mux for multiple ratiometric measurements up to 8khz output rate up to 4khz multiplexing rate selectable speed/resolution: 2 v rms noise at 1.76khz output rate 200nv rms noise at 13.8hz output rate with simultaneous 50/60hz rejection guaranteed modulator stability and lock-up immunity for any input and reference conditions 0.0005% inl, no missing codes autosleep enables 20 a operation at 6.9hz <5 v offset (4.5v < v cc < 5.5v, 40 c to 85 c) differential input and differential reference with gnd to v cc common mode range no latency mode, each conversion is accurate even after a new channel is selected internal oscillatorno external components ltc2447 includes muxout/adcin for external buffering or gain tiny qfn 5mm x 7mm package 24-bit high speed 8-channel ? adcs with selectable multiple reference inputs the ltc ? 2446/ltc2447 4-terminal switching enables multiplexed ratiometric measurements. four sets of se- lectable differential inputs coupled with four sets of differ- ential reference inputs allow multiple rtds, bridges and other sensors to be digitized by a single converter. a fifth differential reference input can be selected for any input channel not requiring ratiometric measurements (ther- mocouples, voltages, current sense, etc.). the flexible input multiplexer allows single-ended or differential in- puts coupled with a slaved reference input or a universal reference input. a proprietary delta-sigma architecture results in absolute accuracy (offset, full-scale, linearity) of 15ppm, noise as low as 200nv rms and speeds as high as 8khz. through a simple 4-wire interface, ten speed/resolution combina- tions can be selected. the first conversion following a speed, resolution, channel change or reference change is valid since there is no settling time between conversions, enabling scan rates of up to 4khz. additionally, a 2x mode can be selected for any speed-enabling output rates up to 8khz with one cycle of latency. , ltc and lt are registered trademarks of linear technology corporation. ltc2446 speed vs rms noise multiple ratiometric measurement system conversion rate (hz) 1 0.1 rms noise ( v) 1 10 100 10 100 24467 ta02 1000 10000 2.8 v at 880hz 280nv at 6.9hz (50/60hz rejection) v cc = 5v v ref = 5v v in + = v in C = 0v 2x speed mode no latency mode variable speed/ resolution 24-bit ? adc + C 19-input 4-output mux ? ? ? ref + v cc ltc2446 in + in C ref C cs sdi sdo sck 24467 ta01 protected by u.s. patents, including 6140950, 6169506, 6208279, 6411242, 6639526
ltc2446/ltc2447 2 24467fa 13 14 15 16 top view 39 uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com ch0 ch1 v ref01 C v ref01 + ch2 gnd refg C refg + v cc nc nc nc nc v ref67 + v ref67 C ch7 ch6 sck sdo cs f o sdi gnd gnd ch3 v ref23 C v ref23 + ch4 ch5 v ref45 C v ref45 + 23 22 21 20 9 10 11 12 order part number absolute axi u rati gs w ww u package/order i for atio uu w (notes 1, 2) supply voltage (v cc ) to gnd .......................C 0.3v to 6v analog input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) reference input pins voltage to gnd .................................... C 0.3v to (v cc + 0.3v) digital input voltage to gnd ........ C 0.3v to (v cc + 0.3v) LTC2446CUHF ltc2446iuhf qfn part marking* 2446 digital output voltage to gnd ..... C 0.3v to (v cc + 0.3v) operating temperature range ltc2446c/ltc2447c .............................. 0 c to 70 c ltc2446i/ltc2447i ........................... C 40 c to 85 c storage temperature range ................. C 65 c to 125 c t jmax = 125 c, ja = 34 c/w exposed pad (pin 39) is gnd must be soldered to pcb *the temperature grade is identified by a label on the shipping container. consult ltc marketing for parts specified with wider operating temperature ranges. order part number ltc2447cuhf ltc2447iuhf qfn part marking* 2447 13 14 15 16 39 top view uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 gnd busy ext gnd gnd gnd com ch0 ch1 v ref01 C v ref01 + ch2 gnd refg C refg + v cc muxoutn adcinn adcinp muxoutp v ref67 + v ref67 C ch7 ch6 sck sdo cs f o sdi gnd gnd ch3 v ref23 _ v ref23 + ch4 ch5 v ref45 C v ref45 + 23 22 21 20 9 10 11 12 t jmax = 125 c, ja = 34 c/w exposed pad (pin 39) is gnd must be soldered to pcb order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ ltc2446/ltc2447 3 24467fa electrical characteristics parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) 24 bits integral nonlinearity v cc = 5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) 5 15 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 3 ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, 2.5 5 v gnd in + = in C v cc (note 12) offset error drift 2.5v ref + v cc , ref C = gnd, 20 nv/ c gnd in + = in C v cc positive full-scale error ref + = 5v, ref C = gnd, in + = 3.75v, in C = 1.25v 10 50 ppm of v ref ref + = 2.5v, ref C = gnd, in + = 1.875v, in C = 0.625v 10 50 ppm of v ref positive full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.2 ppm of v ref / c in + = 0.75ref + , in C = 0.25 ? ref + negative full-scale error ref + = 5v, ref C = gnd, in + = 1.25v, in C = 3.75v 10 50 ppm of v ref ref + = 2.5v, ref C = gnd, in + = 0.625v, in C = 1.875v 10 50 ppm of v ref negative full-scale error drift 2.5v ref + v cc , ref C = gnd, 0.2 ppm of v ref / c in + = 0.25 ? ref + , in C = 0.75 ? ref + total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 15 ppm of v ref 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v 15 ppm of v ref ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 15 ppm of v ref input common mode rejection dc 2.5v ref + v cc , ref C = gnd, 120 db gnd in C = in + v cc the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (notes 3, 4) symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v v in input differential voltage range Cv ref /2 v ref /2 v (in + C in C ) ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd v cc C 0.1v v v ref reference differential voltage range 0.1 v cc v (ref + C ref C ) c s(in+) in + sampling capacitance 2 pf c s(inC) in C sampling capacitance 2 pf c s(ref+) ref + sampling capacitance 2 pf c s(refC) ref C sampling capacitance 2 pf i dc_leak(in+, inC, leakage current, inputs and reference cs = v cc , in + = gnd, in C = gnd, C15 1 15 na ref+, refC) ref + = 5v, ref C = gnd i sample(in+, inC, average input/reference current varies, see applications section na ref+, refC) during sampling t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) a alog i put a u d refere ce uu u ltc2446/ltc2447 4 24467fa ti i g characteristics u w symbol parameter conditions min typ max units v cc supply voltage 4.5 5.5 v i cc supply current conversion mode cs = 0v (note 7) 811 ma sleep mode cs = v cc (note 7) 830 a the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) power require e ts w u the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 4.5v v cc 5.5v 2.5 v cs, f o v il low level input voltage 4.5v v cc 5.5v 0.8 v cs, f o v ih high level input voltage 4.5v v cc 5.5v (note 8) 2.5 v sck v il low level input voltage 4.5v v cc 5.5v (note 8) 0.8 v sck i in digital input current 0v v in v cc C10 10 a cs, f o , ext, soi i in digital input current 0v v in v cc (note 8) C10 10 a sck c in digital input capacitance 10 pf cs, f o c in digital input capacitance (note 8) 10 pf sck v oh high level output voltage i o = C800 a v cc C 0.5v v sdo, busy v ol low level output voltage i o = 1.6ma 0.4v v sdo, busy v oh high level output voltage i o = C800 a (note 9) v cc C 0.5v v sck v ol low level output voltage i o = 1.6ma (note 9) 0.4v v sck i oz hi-z output leakage C10 10 a sdo digital i puts a d digital outputs uu the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range 0.1 20 mhz t heo external oscillator high period 25 10000 ns t leo external oscillator low period 25 10000 ns t conv conversion time osr = 256 0.99 1.13 1.33 ms osr = 32768 126 145 170 ms external oscillator (notes 10, 13) 40 ? osr +170 f eosc (khz) ms f isck internal sck frequency internal oscillator (note 9) 0.8 0.9 1 mhz external oscillator (notes 9, 10) f eosc /10 hz ltc2446/ltc2447 5 24467fa symbol parameter conditions min typ max units d isck internal sck duty cycle (note 9) 45 55 % f esck external sck frequency range (note 8) 20 mhz t lesck external sck low period (note 8) 25 ns t hesck external sck high period (note 8) 25 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 9, 11) 41.6 35.3 30.9 s external oscillator (notes 9, 10) 320/f eosc s t dout_esck external sck 32-bit data output time (note 8) 32/f esck s t 1 cs to sdo low z (note 12) 025ns t 2 cs to sdo high z (note 12) 025ns t 3 cs to sck (note 9) 5 s t 4 cs to sck (notes 8, 12) 25 ns t kqmax sck to sdo valid 25 ns t kqmin sdo hold after sck (note 5) 15 ns t 5 sck setup before cs 50 ns t 6 sck hold after cs 50 ns t 7 sdi setup before sck (note 5) 10 ns t 8 sdi hold after sck (note 5) 10 ns the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 3) ti i g characteristics w u gnd (pins 1, 4, 5, 6, 31, 32, 33): ground. multiple ground pins internally connected for optimum ground current flow and v cc decoupling. connect each one of these pins to a common ground plane through a low impedance connection. all seven pins must be connected to ground for proper operation. busy (pin 2): conversion in progress indicator. this pin is high while the conversion is in progress and goes low indicating the conversion is complete and data is ready. it remains low during the sleep and data output states. at the conclusion of the data output state, it goes high indicating a new conversion has begun. ext (pin 3): internal/external sck selection pin. this pin is used to select internal or external sck for outputting/ inputting data. if ext is tied low, the device is in the external sck mode and data is shifted out of the device under the control of a user applied serial clock. if ext is tied high, the internal serial clock mode is selected. the device generates its own sck signal and outputs this on the sck pin. a framing signal busy (pin 2) goes low indicating data is being output. com (pin 7): the common negative input (in C ) for all single ended multiplexer configurations. the voltage on ch0-ch7 and com pins can have any value between gnd uu u pi fu ctio s note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all voltage values are with respect to gnd. note 3: v cc = 4.5v to 5.5v unless otherwise specified. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; ref + is the positive reference input, ref C is the negative reference input; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to external conversion clock source with f eosc = 10mhz unless otherwise specified. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: the converter uses the internal oscillator. note 8: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as a digital output. in this mode of operation, the sck pin has a total equivalent load capacitance of c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in hz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: guaranteed by design and test correlation. note 13: there is an internal reset that adds an additional 1 s (typ) to the conversion time. ltc2446/ltc2447 6 24467fa contains an enable bit which determines if a new channel/ speed is selected. if this bit is low the following conversion remains at the same speed and selected channel. the serial data input is applied to the device under control of the serial clock (sck) during the data output cycle. the first conversion following a new channel/speed is valid. f o (pin 35): frequency control pin. digital input that controls the internal conversion clock. when f o is con- nected to v cc or gnd, the converter uses its internal oscillator running at 9mhz. the conversion rate is deter- mined by the selected osr such that t conv (ms) = (40 ? osr + 170)/f osc (khz). the first digital filter null is located at 8/t conv , 7khz at osr = 256 and 55hz (simultaneous 50/ 60hz) at osr = 32768. this pin may be driven with a maximum external clock of 10.24mhz resulting in a maxi- mum 8khz output rate (osr = 64, 2x mode). cs (pin 36): active low chip select. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output aborts the data transfer and starts a new conversion. sdo (pin 37): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. this signal is high while the conversion is in progress and goes low once the conversion is complete. sck (pin 38): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as a digital output for the internal serial interface clock during the data output period. in the external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. the serial clock operation mode is determined by the logic level applied to the ext pin. exposed pad (pin 39): ground. the exposed pad on the bottom of the package must be soldered to the pcb ground. for prototyping purposes, this pin may remain floating. C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch7 (pins 8, 9, 12, 13, 16, 17, 20, 21): analog inputs. may be programmed for single-ended or differen- tial mode. v ref01 + (pin 11), v ref01 (pin 10) v ref23 + (pin 15), v ref23 (pin 14), v ref45 + (pin 19), v ref45 (pin 18), v ref67 + (pin 23), v ref67 (pin 22): differential reference inputs. the voltage on these pins can be anywhere between 0v and v cc as long as the positive reference input (v ef01 + , v ref23 + , v ref45 + , v ref67 + ) is greater than the corresponding negative reference input (v ref01 C , v ref23 C , v ref45 C , v ref67 C ) by at least 100mv. nc (pins 24, 25, 26, 27): ltc2446 no connect. these pins can either be tied to ground or left floating. muxoutp (pin 24): ltc2447 positive input channel multiplexer output. used to drive the input to an external buffer/amplifier for the selected positive input signal (in + ). adcinp (pin 25): ltc2447 positive adc input. tie to output of buffer/amplifier driven by muxoutp. adcinn (pin 26): ltc2447 negative adc input. tie to output of buffer/amplifier driven by muxoutn. muxoutn (pin 27): ltc2447 negative input channel multiplexer output. used to drive the input to an external buffer/amplifier for the selected negative input signal (in C ). v cc (pin 28): positive supply voltage. bypass to gnd with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor as close to the part as possible. v refg + (pin 29), v refg (pin 30): global reference input. this differential reference input can be used for any input channel selected through a single bit in the digital input word. sdi (pin 34): serial data input. this pin is used to select the speed, 1x or 2x mode, resolution, input channel and reference input for the next conversion cycle. at initial power-up, the default mode of operation is ch0-ch1, v ref01 , osr of 256, and 1x mode. the serial data input pi fu ctio s uuu ltc2446/ltc2447 7 24467fa test circuits fu ctio al block diagra uu w figure 1. functional block diagram applicatio s i for atio wu u u converter operation converter operation cycle the ltc2446/ltc2447 are multichannel, multireference high speed, delta-sigma analog-to-digital converters with an easy to use 3- or 4-wire serial interface (see figure 1). their operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output/ input (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data output (sdo), serial clock (sck) and chip select (cs). the interface, timing, opera- tion cycle and data out format is compatible with linears entire family of ? converters. initially, the ltc2446/ltc2447 perform a conversion. once the conversion is complete, the device enters the figure 2. ltc2446/ltc2447 state transition diagram autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator serial interface gnd v cc ch0 ch1 ? ? ? ? ? ? ch7 com in + ref + ref C in C input/reference mux sdo sck v refg + v refg C v ref67 + v ref67 C v ref01 + v ref01 C cs sdi f o (int/ext) 24467 f01 convert sleep no yes channel select reference select speed select data output power up in + =ch0, in C =ch1 ref + = v refo1 + , ref C = v ref01 C osr=256,1x mode 24467 f02 cs = low and sck 1.69k sdo 24467 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 24467 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc ltc2446/ltc2447 8 24467fa sleep state. while in this sleep state, power consumption is reduced below 10 a. the part remains in the sleep state as long as cs is high. the conversion result is held indefinitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result while operating in the 1x mode. the data output cor- responds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the con- trol of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32 bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs, sck and ext pins, the ltc2446/ltc2447 offer several flexible modes of opera- tion (internal or external sck). these various modes do not require programming configuration registers; more- over, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the ltc2446/ltc2447 data output has no latency, filter settling delay or redundant data associated with the conversion cycle while operating in the 1x mode. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages and references is easy. speed/resolution adjustments may be made seamlessly between two conversions without settling errors. the ltc2446/ltc2447 perform offset and full-scale cali- brations every conversion cycle. this calibration is trans- parent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. power-up sequence the ltc2446/ltc2447 automatically enter an internal reset state when the power supply voltage v cc drops applicatio s i for atio wu u u below approximately 2.2v. this feature guarantees the integrity of the conversion result and of the serial inter- face mode selection. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. the conversion imme- diately following a por is performed on the input channel in + = ch0, in C = ch1, ref + = v ref01 + , ref C v ref01 C at an osr = 256 in the 1x mode. following the por signal, the ltc2446/ltc2447 start a normal conversion cycle and follow the succession of states described above. the first conversion result following por is accurate within the specifications of the device if the power supply voltage is restored within the operating range (4.5v to 5.5v) before the end of the por time interval. reference voltage range these converters accept truly differential external refer- ence voltages. each set of five reference inputs may be independently driven to any common mode voltage over the entire supply range of the device (gnd to v cc ). for correct converter operation, each positive reference pin ref + (v ref01 + , v ref23 + , v ref45 + , v ref67 + , v refg + ) must be more positive than its corresponding negative refer- ence pin ref C (v ref01 C , v ref23 C , v ref45 C , v ref67 C , v refg C ) by at least 100mv. the ltc2446/ltc2447 can accept a differential reference from 0.1v to v cc on each set of reference input pins. the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in micro- volts is nearly constant with reference voltage. a decrease in reference voltage will not significantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the converters overall inl performance. input voltage range the analog input is truly differential with an absolute/ common mode range for the ch0-ch7 and com input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2446/ltc2447 ltc2446/ltc2447 9 24467fa c onvert the bipolar differential input signal, v in = in + C in C (where in + and in C are the selected input channels), from C fs = C 0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + C ref C (ref + and ref C are the selected references). outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. muxout/adcin there are two differences between the ltc2446 and the ltc2447. the first is the rms noise performance. for a given osr, the ltc2447 noise level is approximately 2 times lower (0.5 effective bits)than that of the ltc2446. the second difference is the ltc2447 includes muxout/ adcin pins. these pins enable an external buffer or gain block to be inserted between the selected input channel of the multiplexer and the input to the adc. since the buffer is driven by the output of the multiplexer, only one circuit is required for all 8 input channels. additionally, the transparent calibration feature of the ltc244x family automatically removes the offset errors of the external buffer. in order to achieve optimum performance, the muxout and adcin pins should not be shorted together. in appli- cations where the muxout and adcin need to be shorted together, the ltc2446 should be used because the muxout and adcin are internally connected for opti- mum performance. output data format the ltc2446/ltc2447 serial output data stream is 32 bits long. the first 3 bits represent status information indicat- ing the sign and conversion state. the next 24 bits are the conversion result, msb first. the remaining 5 bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. in the case of ultrahigh resolution modes, more than 24 effective bits of performance are possible (see table 4). under these conditions, sub lsbs are included in the conversion result and represent useful information beyond the 24-bit level. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). bit 31 (first output bit) is the end of conversion (eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indi- cator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most significant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2446/ltc2447 status bits bit 31 bit 30 bit 29 bit 28 input range eoc dmy sig msb v in 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0001 v in < C 0.5 ? v ref 0000 bits 28-5 are the 24-bit conversion result msb first. bit 5 is the least significant bit (lsb). bits 4-0 are sub lsbs below the 24-bit level. bits 4-0 may be included in averaging or discarded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance and sck is ignored. in order to shift the conversion result out of the device, cs must first be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 31 (eoc) can be captured on the first applicatio s i for atio wu u u ltc2446/ltc2447 10 24467fa msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 24467 f03 sig bit 29 0 bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl glbl a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 +fs, the conversion result is clamped to the value corre- sponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. serial interface pins the ltc2446/ltc2447 transmit the conversion results and receive the start of conversion command through a synchronous 3- or 4-wire interface. during the conver- sion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed, resolution and input channel. rising edge of sck. bit 30 is shifted out of the device on the first falling edge of sck. the final data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is maintained within the C 0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than table 2. ltc2446/ltc2447 output data format differential input voltage bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 0 v in * eoc dmy sig msb v in * 0.5 ? v ref ** 0 0110 0 00 0.5 ? v ref ** C 1lsb 0 0101 1 11 0.25 ? v ref ** 0 0101 0 00 0.25 ? v ref ** C 1lsb 0 0100 1 11 0 0 0100 0 00 C1lsb 0 0011 1 11 C 0.25 ? v ref ** 0 0011 0 00 C 0.25 ? v ref ** C 1lsb 0 0010 1 11 C 0.5 ? v ref ** 0 0010 0 00 v in * < C0.5 ? v ref ** 0 0001 1 11 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . applicatio s i for atio wu u u figure 3. sdi speed/resolution, channel selection, and data output timing ltc2446/ltc2447 11 24467fa serial clock input/output (sck) the serial clock signal present on sck (pin 38) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2446/ltc2447 create their own serial clock. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected by tying ext (pin 3) low for external sck and high for internal sck. serial data output (sdo) the serial data output pin, sdo (pin 37), provides the result of the last conversion as a serial bit stream (msb first) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 36) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the first rising edge of sck occurs while cs = low. chip select input (cs) the active low chip select, cs (pin 36), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. the ltc2446/ltc2447 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state. serial data input (sdi) the serial data input (sdi, pin 34) is used to select the speed/resolution input channel and reference of the ltc2446/ltc2447. sdi is programmed by a serial input data stream under the control of sck during the data output cycle, see figure 3. initially, after powering up, the device performs a conver- sion with in + = ch0, in C = ch1, ref + = v ref01 + , ref C = v ref01 C , osr = 256 (output rate nominally 880hz), and 1x speed mode (no latency). once this first conversion is complete, the device enters the sleep state and is ready to output the conversion result and receive the serial data input stream programming the speed/resolution, input channel and reference for the next conversion. at the conclusion of each conversion cycle, the device enters this state. in order to change the speed/resolution, reference or input channel, the first 3 bits shifted into the device are 101. this is compatible with the programming sequence of the ltc2414/ltc2418/ltc2444/ltc2445/ltc2448/ ltc2449. if the sequence is set to 000 or 100, the follow- ing input data is ignored (dont care) and the previously selected speed/resolution, channel and reference remain valid for the next conversion. combinations other than 101, 100, and 000 of the 3 control bits should be avoided. if the first 3 bits shifted into the device are 101, then the following 5 bits select the input channel/reference for the following conversion (see table 3). the next 5 bits select the speed/resolution and mode 1x (no latency) 2x (double output rate with one conversion latency), see table 4. if these 5 bits are set to all 0s, the previous speed remains selected for the next conversion. this is useful in applica- tions requiring a fixed output rate/resolution but need to change the input channel or reference. in this case, the timing and input sequence is compatible with the ltc2414/ ltc2418. when an update operation is initiated (the first 3 bits are 101) the next 5 bits are the channel/reference address. the first bit, sgl, determines if the input selection is differen- tial (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent channels can be selected to form a differential input. for sgl = 1, one of 8 channels is selected as the positive input. the negative input is com for all single ended operations. the global v ref bit (glbl) is used to determine which reference is selected. glbl = 0 selects the individual reference slaved to a given channel. each set of channels has a corresponding differential input refer- ence. if glbl = 1, a global reference v refg + /v refg C is selected. the global reference input may be used for any input channel selected. table 3 shows a summary of input/ reference selection. the remaining bits (odd, a1, a0) determine which channel is selected. applicatio s i for atio wu uu ltc2446/ltc2447 12 24467fa table 3. channel selection for the ltc2446/ltc2447 mux address channel input reference input odd/ sgl sign glbl a1 a0 0 1 2 3 4 5 6 7 com 01 + 01 23 + 23 45 + 45 67 + 67 g + g *0 0 0 0 0 in + in C ref + ref C 00001 in + in C ref + ref C 00010 in + in C ref + ref C 00011 in + in C ref + ref C 01000in C in + ref + ref C 01001 in C in + ref + ref C 01010 in C in + ref + ref C 01011 in C in + ref + ref C 10000in + in C ref + ref C 10001 in + in C ref + ref C 10010 in + in C ref + ref C 10011 in + inC ref + ref C 11000 in + in C ref + ref C 11001 in + in C ref + ref C 11010 in + in C ref + ref C 11011 in + in C ref + ref C 00100in + in C ref + ref C 00101 in + in C ref + ref C 00110 in + in C ref + ref C 00111 in + in C ref + ref C 01100in C in + ref + ref C 01101 in C in + ref + ref C 01110 in C in + ref + ref C 01111 in C in + ref + ref C 10100in + in C ref + ref C 10101 in + in C ref + ref C 10110 in + in C ref + ref C 10111 in + in C ref + ref C 11100 in + in C ref + ref C 11101 in + in C ref + ref C 11110 in + in C ref + ref C 11111 in + in C ref + ref C *default at power up applicatio s i for atio wu u u ltc2446/ltc2447 13 24467fa applicatio s i for atio wu uu table 4. ltc2446/ltc2447 speed/resolution selection conversion rate internal external rms rms 9mhz 10.24mhz noise noise enob enob osr3 osr2 osr1 osr0 twox clock clock ltc2446 ltc2447 ltc2446 ltc2447 osr latency 00000 k eep previous speed/resolution 000103. 52khz 4khz 23 v23 v 17 17 64 none 001001. 76khz 2khz 4.4 v 3.5 v 20.1 20.1 128 none 00110 880hz 1khz 2.8 v2 v 20.8 21.3 256 none 01000 440hz 500hz 2 v 1.4 v 21.3 21.8 512 none 01010 220hz 250hz 1.4 v1 v 21.8 22.4 1024 none 01100 110hz 125hz 1.1 v 750nv 22.1 22.9 2048 none 01110 55hz 62.5hz 720nv 510nv 22.7 23.4 4096 none 10000 27.5hz 31.25hz 530nv 375nv 23.2 24 8192 none 1001013. 75hz 15.625hz 350nv 250nv 23.8 24.4 16384 none 111106. 875hz 7.8125hz 280nv 200nv 24.1 24.6 32768 none 00001 k eep previous speed/resolution 000117. 04khz 8khz 23 v23 v 17 17 64 1 cycle 001013. 52khz 4khz 4.4 v 3.5 v 20.1 20.1 128 1 cycle 001111. 76khz 2khz 2.8 v2 v 20.8 21.3 256 1 cycle 01001 880hz 1khz 2 v 1.4 v 21.3 21.8 512 1 cycle 01011 440hz 500hz 1.4 v1 v 21.8 22.4 1024 1 cycle 01101 220hz 250hz 1.1 v 750nv 22.1 22.9 2048 1 cycle 01111 110hz 125hz 720nv 510nv 22.7 23.4 4096 1 cycle 10001 55hz 62.5hz 530nv 375nv 23.2 24 8192 1 cycle 10011 27.5hz 31.25hz 350nv 250nv 23.8 24.4 16384 1 cycle 1111113. 75hz 15.625hz 280nv 200nv 24.1 24.6 32768 1 cycle ltc2446/ltc2447 14 24467fa speed multiplier mode in addition to selecting the speed/resolution, a speed multiplier mode is used to double the output rate while maintaining the selected resolution. the last bit of the 5-bit speed/resolution control word (twox, see table 4) deter- mines if the output rate is 1x (no speed increase) or 2x (double the selected speed). while operating in the 1x mode, the device combines two internal conversions for each conversion result in order to remove the adc offset. every conversion cycle, the offset and offset drift are transparently calibrated greatly simpli- fying the user interface. the conversion result has no latency. the first conversion following a newly selected speed/resolution and/or input/reference is valid. this is identical to the operation of the ltc2440, ltc2444, ltc2445, ltc2448, ltc2449, ltc2414 and ltc2418. while operating in the 2x mode, the device performs a running average of the last two conversion results. this automatically removes the offset and drift of the device while increasing the output rate by 2x. the resolution (noise) remains the same as the 1x mode. if a new channel/reference is selected, the conversion result is valid for all conversions after the first conversion (one cycle latency). if a new speed/resolution is selected, the first conversion result is valid but the resolution (noise) is a function of the running average. all subsequent conver- sion results are valid. if the mode is changed from either 1x to 2x or 2x to 1x without changing the resolution or channel, the first conversion result is valid. if an external buffer/amplifier circuit is used for the ltc2447, the 2x mode can be used to increase the settling time of the amplifier between readings. while operating in the 2x mode, the multiplexer output (input to the external buffer/amplifier) is switched at the end of each conversion cycle. prior to concluding the data out/in cycle, the analog multiplexer output is switched. this occurs at the end of the conversion cycle (just prior to the data output cycle) for auto calibration. the time required to read the conver- sion enables more settling time for the external buffer/ amplifier. the offset/offset drift of the external amplifiers are automatically removed by the converters auto calibra- tion sequence for both the 1x and 2x speed modes. while operating in the 1x mode, if a new input channel/ reference is selected the multiplexer is switched on the falling edge of the 14th sck (once the complete data input word is programmed). the remaining data output se- quence time can be used to allow the external buffer/ amplifier to settle. busy the busy output (pin 2) is used to monitor the state of conversion, data output and sleep cycle. while the part is converting, the busy pin is high. once the conversion is complete, busy goes low indicating the conversion is complete and data out is ready. the part now enters the low power sleep state. busy remains low while data is shifted out of the device and sdi is shifted into the device. it goes high at the conclusion of the data input/output cycle indicating a new conversion has begun. this rising edge may be used to flag the completion of the data read cycle. serial interface timing modes the ltc2446/ltc2447s 3- or 4-wire interface is spi and microwire compatible. this interface offers several flex- ible modes of operation. these include internal/external serial clock, 3- or 4-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. refer to table 5 for a summary. table 5. ltc2446/ltc2447 interface timing modes conversion data connection sck cycle output and configuration source control control waveforms external sck, single cycle conversion external cs and sck cs and sck figures 4, 5 external sck, 3-wire i/o external sck sck figure 6 internal sck, single cycle conversion internal cs cs figures 7, 8 internal sck, 3-wire i/o, continuous conversion internal continuous internal figure 9 applicatio s i for atio wu uu ltc2446/ltc2447 15 24467fa external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 4. the serial clock mode is selected by the ext pin. to select the external serial clock mode, ext must be tied low. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 (busy = 1) while a conversion is in progress and eoc = 0 (busy = 0) if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state (eoc = 0), its conversion result is held in an internal static shift regis- ter. the device remains in the sleep state until the first rising edge of sck is seen. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the first rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) and busy goes high indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z and busy monitored for the completion of a conversion. figure 4. external serial clock, single cycle operation applicatio s i for atio wu uu msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 24467 f04 sig bit 29 0 bit 30 eoc hi-z cs sck (external) sdi sdo busy bit 31 1 0 en sgl glbl a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc v cc f o ref67 + ref67 C ch0 ch1 ch2 ch7 com refg + refg C ref01 + ref01 C sck sdi sdo cs gnd 28 29 30 11 10 35 24 23 8 9 12 22 7 38 37 1,4,5,6,31,32,33 36 34 user selectable references 0.1v to v cc analog inputs . . . . . . 2 = external oscillator = internal oscillator 1 f 4.5v to 5.5v ltc2446 4-wire spi interface busy ltc2446/ltc2447 16 24467fa output sequence is aborted prior to the 13th rising edge of sck, the new input data is ignored, and the previously selected speed/resolution and channel are used for the next conversion cycle. this is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conver- sion. if a new channel is being programmed, the rising edge of cs must come after the 14th falling edge of sck in order to store the data input sequence. cs sck (external) sdi sdo busy 123456 15 msb bit 28 bit 27 bit 26 bit 25 sig bit 29 0 bit 30 eoc hi-z hi-z bit 31 24467 f05 conversion sleep sleep data output data output conversion conversion test eoc don't care don't care don't care v cc f o ref67 + ref67 C ch0 ch1 ch2 ch7 com refg + refg C ref01 + ref01 C sck sdi sdo cs gnd 28 29 30 11 10 35 24 23 8 9 12 22 7 38 37 1,4,5,6,31,32,33 36 34 user selectable references 0.1v to v cc analog inputs . . . . . . 2 = external oscillator = internal oscillator 1 f 4.5v to 5.5v ltc2446 4-wire spi interface busy as described above, cs may be pulled low at any time in order to monitor the conversion status on the sdo pin. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the fifth falling edge and the 32nd falling edge of sck, see figure 5. on the rising edge of cs, the device aborts the data output state and imme- diately initiates a new conversion. thirteen serial input data bits are required in order to properly program the speed/resolution and input/reference channel. if the data applicatio s i for atio wu u u figure 5. external serial clock, reduced output data length ltc2446/ltc2447 17 24467fa applicatio s i for atio wu u u external serial clock, 3-wire i/o this timing mode utilizes a 3-wire serial i/o interface. the conversion result is shifted out of the device by an exter- nally generated serial clock (sck) signal, see figure 6. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected by tying ext low. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. conversely, busy (pin 2) may be used to monitor the status of the conversion cycle. eoc or busy may be used as an interrupt to an external controller figure 6. external serial clock, cs = 0 operation (3-wire) indicating the conversion result is ready. eoc = 1 (busy = 1) while the conversion is in progress and eoc = 0 (busy = 0) once the conversion enters the low power sleep state. on the falling edge of eoc/busy, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the first rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the first rising edge of sck. on the 32nd falling edge of sck, sdo and busy go high (eoc = 1) indicating a new conversion has begun. cs sck (external) sdi sdo busy 24467 f06 conversion sleep data output conversion msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb sig bit 29 0 bit 30 eoc bit 31 1 0 en sgl glbl a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 don't care don't care v cc f o ref67 + ref67 C ch0 ch1 ch2 ch7 com refg + refg C ref01 + ref01 C sck sdi sdo cs gnd 28 29 30 11 10 35 24 23 8 9 12 22 7 38 37 1,4,5,6,31,32,33 36 34 user selectable references 0.1v to v cc analog inputs . . . . . . 2 = external oscillator = internal oscillator 1 f 4.5v to 5.5v ltc2446 3-wire spi interface busy ltc2446/ltc2447 18 24467fa internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 7. in order to select the internal serial clock timing mode, the ext pin must be tied high. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. alternatively, busy (pin 2) may be used to monitor the status of the conversion in progress. busy is high during the conver- figure 7. internal serial clock, single cycle operation sion and goes low at the conclusion. it remains low until the result is read from the device. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled high before the first rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 500ns. if cs is pulled high before time t eoctest , the device remains in the sleep state. the conversion result is held in the internal static shift register. applicatio s i for atio wu uu msb bit 28 bit 27 bit 26 bit 25 bit 24 bit 23 bit 22 bit 21 bit 20 bit 19 bit 0 lsb hi-z 244676 f07 sig bit 29 0 bit 30 eoc hi-z cs sck sdi sdo busy bit 31 1 0 en sgl glbl a1 a0 osr3 osr2 osr1 osr0 twox odd 1234567891011121314 32 conversion sleep data output conversion test eoc test eoc don't care don't care ltc2446/ltc2447 21 24467fa figure 11. ltc2446/ltc2447 normal mode rejection (internal oscillator) figure 10. ltc2446/ltc2447 normal mode rejection (internal oscillator) applicatio s i for atio wu u u table 6. osr vs notch frequency (f n ) (with internal oscillator running at 9mhz) osr notch (f n ) 64 28.16khz 128 14.08khz 256 7.04khz 512 3.52khz 1024 1.76khz 2048 880hz 4096 440hz 8192 220hz 16384 110hz 32768* 55hz *simultaneous 50/60hz rejection normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over con- ventional adcs is on-chip digital filtering. combined with a large oversampling ratio, the ltc2446/ltc2447 signifi- cantly simplify antialiasing filter requirements. the ltc2446/ltc2447s speed/resolution is determined by the over sample ratio (osr) of the on-chip digital filter. the osr ranges from 64 for 3.5khz output rate to 32,768 for 6.9hz (in 1x mode) output rate. the value of osr and the sample rate f s determine the filter characteristics of the device. the first null of the digital filter is at f n and multiples of f n where f n = f s /osr, see figure 10 and table 6. the rejection at the frequency f n 14% is better than 80db, see figure 11. differential input signal frequency (hz) 0 C60 C40 0 180 24467 f10 C80 C100 60 120 240 C120 C140 C20 normal mode rejection (db) sinc 4 envelope differential input signal frequency (hz) 47 C140 normal mode rejection (db) C130 C120 C110 C100 51 55 59 63 24467 f11 C90 C80 49 53 57 61 if f o is grounded, f s is set by the on-chip oscillator at 1.8mhz 5% (over supply and temperature variations). at an osr of 32,768, the first null is at f n = 55hz and the no latency output rate is f n /8 = 6.9hz. at the maximum osr, the noise performance of the device is 280nv rms (ltc2446) and 200nv rms (ltc2447) with better than 80db rejection of 50hz 2% and 60hz 2%. since the osr is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. the first multiple of f s occurs at 55hz ? 32,768 = 1.8mhz, see figure 12. the first null becomes f n = 7.04khz with an osr of 256 (an output rate of 880hz) and f o grounded. while the null has shifted, the sample rate remains constant. as a result of constant modulator sampling rate, the linearity, figure 12. ltc2446/ltc2447 normal mode rejection (internal oscillator) differential input signal frequency (hz) 0 C60 C40 0 24467 f12 C80 C100 1000000 2000000 C120 1.8mhz C140 C20 normal mode rejection (db) rejection > 120db ltc2446/ltc2447 22 24467fa offset and full-scale performance remain unchanged as does the first multiple of f s . the sample rate f s and null f n , may also be adjusted by driving the f o pin with an external oscillator. the sample rate is f s = f eosc /5, where f eosc is the frequency of the clock applied to f o . combining a large osr with a reduced sample rate leads to notch frequencies f n near dc while maintaining simple antialiasing requirements. a 100khz clock applied to f o results in a null at 0.6hz plus all harmonics up to 20khz, see figure 13. this is useful in applications requiring digitalization of the dc component of a noisy input signal and eliminates the need of placing a 0.6hz filter in front of the adc. figure 13. ltc2446/ltc2447 normal mode rejection (external oscillator at 90khz) applicatio s i for atio wu uu differential input signal frequency (hz) 0 C40 C20 0 8 24467 f13 C60 C80 246 10 C100 C120 C140 normal mode rejection (db) multiplexer. the unique no latency architecture allows seamless changes in both input channel and reference while the absolute accuracy ensures excellent matching between both analog input channels and reference chan- nels. any set of inputs (differential or single-ended) can perform a conversion with one of two references. for bridges, rtds and other ratiometric devices, each set of channels can perform a conversion with respect to a unique reference voltage. for thermocouples, voltage sense, current sense and other absolute sensors, each set of channels can perform a conversion with respect to a single global reference voltage (see figure 15). this allows users to measure both multiple absolute and multiple ratio metric sensors with the same device in such applications as flow, gas chromatography, multiple rtds or bridges, or universal data acquisition. average input current the ltc2446 switches the input and reference to a 2pf capacitor at a frequency of 1.8mhz. a simplified equivalent circuit is shown in figure 16. the sample capacitor for the ltc2447 is 4pf, and its average input current is externally buffered from the input source. the average input and reference currents can be ex- pressed in terms of the equivalent input resistance of the sample capacitor, where: req = 1/(f sw ? ceq). an external oscillator operating from 100khz to 20mhz can be implemented using the ltc1799 (resistor set sot-23 oscillator), see figure 14. by floating pin 4 (div) of the ltc1799, the output oscillator frequency is: f mhz k r osc set = ? ? ? ? ? ? 10 10 10 ? ? the normal mode rejection characteristic shown in figure 13 is achieved by applying the output of the ltc1799 (with r set = 100k) to the f o pin on the ltc2446/ltc2447 with sdi tied high (osr = 32768). multiple ratiometric and absolute measurements the ltc2446/ltc2447 combine a high precision, high speed delta-sigma converter with a versatile front-end figure 14. simple external clock source 24467 f14 0.1 f ltc1799 out div set gnd v + r set nc v cc f o ref67 + ref67 C ch0 ch1 ch2 ch7 com refg + refg C ref01 + ref01 C sck sdi sdo cs gnd 28 29 30 11 10 35 24 23 8 9 12 22 7 38 37 1,4,5,6,31,32,33 36 34 user selectable references 0.1v to v cc analog inputs . . . . . . 2 1 f 4.5v to 5.5v ltc2446 4-wire spi interface busy ltc2446/ltc2447 23 24467fa applicatio s i for atio wu u u figure 15. versatile 4-way multiplexer measures multiple ratiometric/absolute sensors figure 16. ltc2446 input structure when using the internal oscillator, f sw is 1.8mhz and the equivalent resistance is approximately 110k ? . input bandwidth and frequency rejection the combined effect of the internal sinc 4 digital filter and the digital and analog autocalibration circuits determines the ltc2446/ltc2447 input bandwidth and rejection characteristics. the digital filters response can be ad- justed by setting the oversample ratio (osr) through the spi interface or by supplying an external conversion clock to the f o pin. table 7 lists the properties of the ltc2446/ltc2447 with various combinations of oversample ratio and clock fre- quency. understanding these properties is the key to fine tuning the characteristics of the ltc2446/ltc2447 to the application. v refg + 10 f v refo1 + v refo1 C rtd ch0 ch1 ltc2446 v ref v cc v ref23 + v ref23 C in + variable speed resolution 24-bit ? adc ref + in C ref C rtd ratiometric absolute vs v refg bridge ch2 ch3 v ref45 + v ref45 C ch4 ch5 com v refg 24467 f15 ch6 ch7 cs + C sdi sdo sck v ref + v in + v cc r sw (typ) 500 ? i leak i leak v cc i leak i leak v cc r sw (typ) 500 ? c eq 5pf (typ) (c eq = 2pf sample cap + parasitics) r sw (typ) 500 ? i leak i in + v in C i in C i ref + i ref C 24467 f16 i leak v cc i leak i leak switching frequency f sw = 1.8mhz internal oscillator f sw = f eosc /5 external oscillator v ref C r sw (typ) 500 ? mux mux ltc2446/ltc2447 24 24467fa maximum conversion rate the maximum conversion rate is the fastest possible rate at which conversions can be performed. first notch frequency this is the first notch in the sinc 4 portion of the digital filter and depends on the f o clock frequency and the oversample ratio. rejection at this frequency and its multiples (up to the modulator sample rate of 1.8mhz) exceeds 120db. this is 8 times the maximum conversion rate. effective noise bandwidth the ltc2446/ltc2447 has extremely good input noise rejection from the first notch frequency all the way out to the modulator sample rate (typically 1.8mhz). effective noise bandwidth is a measure of how the adc will reject wideband input noise up to the modulator sample rate. the example on the following page shows how the noise rejection of the ltc2446/ltc2447 reduces the effective noise of an amplifier driving its input. example: if an amplifier (e.g. lt1219) driving the input of an ltc2446/ltc2447 has wideband noise of 33nv/ hz, band-limited to 1.8mhz, the total noise entering the adc input is: 33nv/ hz ? 1.8mhz = 44.3 v. applicatio s i for atio wu u u when the adc digitizes the input, its digital filter rejects the wideband noise from the input signal. the noise reduction depends on the oversample ratio which defines the effec- tive bandwidth of the digital filter. at an oversample of 256, the noise bandwidth of the adc is 787hz which reduces the total amplifier noise to: 33nv/ hz ? 787hz = 0.93 v. the total noise is the rms sum of this noise with the 2 v noise of the adc at osr=256. (0.93 v) 2 + (2uv) 2 = 2.2 v. increasing the oversample ratio to 32768 reduces the noise bandwidth of the adc to 6.2hz which reduces the total amplifier noise to: 33nv/ hz ? 6.2hz = 82nv. the total noise is the rms sum of this noise with the 200nv noise of the adc at osr = 32768. (82nv) 2 + (200nv) 2 = 216nv. in this way, the digital filter with its variable oversampling ratio can greatly reduce the effects of external noise sources. table 7. performance vs over-sample ratio maximum first notch effective ?db over- conversion rate frequency noise bw point (hz) sample *rms *rms enob internal internal internal internal ratio noise noise (v ref = 5v) 9mhz external 9mhz external 9mhz external 9mhz external (osr) ltc2446 ltc2447 ltc2446 ltc2447 clock f o clock f o clock f o clock f o 64 23 v23 v 17 17 3515.6 f o /2560 28125 f o /320 3148 f o /5710 1696 f o /5310 128 4.5 v 3.5 v 20.1 20 1757.8 f o /5120 14062.5 f o /640 1574 f o /2860 848 f o /10600 256 2.8 v2 v 20.8 21.3 878.9 f o /10240 7031.3 f o /1280 787 f o /1140 424 f o /21200 512 2 v 1.4 v 21.3 21.8 439.5 f o /20480 3515.6 f o /2560 394 f o /2280 212 f o /42500 1024 1.4 v1 v 21.8 22.4 219.7 f o /40960 1757.8 f o /5120 197 f o /4570 106 f o /84900 2048 1.1 v 750nv 22.1 22.9 109.9 f o /81920 878.9 f o /1020 98.4 f o /9140 53 f o /170000 4096 720nv 510nv 22.7 23.4 54.9 f o /163840 439.5 f o /2050 49.2 f o /18300 26.5 f o /340000 8192 530nv 375nv 23.2 24 27.5 f o /327680 219.7 f o /4100 24.6 f o /36600 13.2 f o /679000 16384 350nv 250nv 23.8 24.4 13.7 f o /655360 109.9 f o /8190 12.4 f o /73100 6.6 f o /1358000 32768 280nv 200nv 24.1 24.6 6.9 f o /1310720 54.9 f o /16380 6.2 f o /146300 3.3 f o /2717000 *adc noise increases by approximately 2 when osr is decreased by a factor of 2 for osr 32768 to osr 256. the adc noise at osr 128 and osr 64 include effects from int ernal modulator quantization noise. ltc2446/ltc2447 25 24467fa automatic offset calibration of external buffers/amplifiers the ltc2447 enables an external amplifier to be inserted between the multiplexer output and the adc input. this enables one external buffer/amplifier circuit to be shared between all nine analog inputs (eight single-ended or four differential). the ltc2447 performs an internal offset calibration every conversion cycle in order to remove the offset and drift of the adc. this calibration is performed through a combination of front end switching and digital processing. since the external amplifier is placed between the multiplexer and the adc, it is inside the correction loop. this results in automatic offset correction and offset drift removal of the external amplifier. the lt1368 is an excellent amplifier for this function. it has rail-to-rail inputs and outputs, and it operates on a single 5v supply. its open-loop gain is 1m and its input bias current is 10na. it also requires at least a 0.1 f load capacitor for compensation. it is this feature that sets it apart from other amplifiersthe load capacitor applicatio s i for atio wu u u C + C + 5v 0v 1/2 lt1368 1/2 lt1368 1 2 3 4 5 6 7 8 *lt1368 requires 0.1 f output compensation capacitor mux muxoutn muxoutp adcinp adcinn 9 24467 f17 (external amplifiers) ltc2447 ch0-ch6/ com mux 10 five differential reference inputs sdi sck sdo cs 0.1 f* offsets and 1/f noise of external signal conditioning circuits are automatically cancelled 0.1 f* high speed ? adc ref + ref C figure 17. external buffers provide high impedance inputs and amplifier offsets are cancelled attenuates sampling glitches from the ltc2447 adcin terminal, allowing it to achieve full performance of the adc with high impedance at the multiplexer inputs. another benefit of the lt1368 is that it can be powered from supplies equal to or greater than that of the adc. this can allow the inputs to span the entire absolute maximum of gnd C 0.3v to v cc + 0.3v. using a positive supply of 7.5v to 10v and a negative supply of C2.5 to C5v gives the amplifier plenty of headroom over the ltc2447 input range. interfacing sensors to the ltc2447 figure 18 shows a few of the ways that the multiple reference inputs of the ltc2447 greatly simplify sensor interfacing. each of the four references is fully differential and has a differential range of 100mv to 5v. this opens up many possibilities for sensing voltages and currents, eliminating much of the analog signal conditioning cir- cuitry required for interfacing to conventional adcs. ltc2446/ltc2447 26 24467fa applicatio s i for atio wu uu figure 18a is a standard 350 ? , voltage excited strain gauge with sense wires for the excitation voltage. ref01 + and ref01 C sense the excitation voltage at the gauge, compen- sating for voltage drop along the high current excitation supply wires. this can be a significant error, as the exci- tation current is 14ma when excited with 5v. reference loading capacitors at the adc are necessary to average the reference current during sampling. both adc inputs are always close to mid-reference, and hence close to mid- supply when using 5v excitation. figure 18b is a novel way to interface the ltc2447 to a bridge that is specified for constant current excitation. the fujikura fpm-120pg is a 120psig pressure sensor that is not trimmed for absolute accuracy, but is temperature compen- sated for low drift when excited by a constant current source. the ltc2447s fully differential reference allows sensing the excitation current with a resistor in series with the bridge excitation. changes in ambient temperature and supply voltage will cause the current to vary, but the ltc2447 compensates by using the current sense voltage as its reference. the input common mode will be slightly higher than mid-reference, but still far enough away from the positive supply to eliminate concerns about the buffer amplifiers headroom. figure 18c is an omega 44018 linear output thermistor. two fixed resistors linearize the output from the thermistors. the recommended 5700 ? series resistor is broken up into two 2850 ? resistors to give a differential output centered around mid-reference. this ensures that the buffer ampli- fiers have enough headroom at the negative supply. note that the excitation is 3v, the maximum recommended by the manufacturer to prevent self-heating errors. the ltc2447 senses this reference voltage. figure 18d shows a standard 100 ? platinum rtd. this circuit shows how to use the ltc2447 to make a direct resistance measurement, where the output code is the rtd resistance divided by the reference resistance. a 500 ? sense resistor allows measurement of resistance up to 250 ? . (a standard = 0.00385 rtd has a resistance of 247.09 ? at 400 c.) the ltc2446 multiplexes rail-to-rail inputs directly to the adc modulator and is suitable for low impedance resistive sources such as 100 ? rtds and 350 ? strain gauges that are located close to the adc. in applications where the source resistance is high or the source is located more than 5cm to 10cm from the adc, the ltc2447 (with an lt1368 buffer) is appropriate. the ltc2447 automatically removes offset, drift and 1/f noise of the lt ? 1368. one consideration for single supply applications is that both adc inputs should always be at least 100mv from the lt1368s supply rails. all of the applications shown in figure 18 are designed to keep both analog inputs far enough away from ground and v cc so that the lt1368 can operate on the same 5v supply as the ltc2447. although the lt1368 has rail-to-rail inputs and outputs, these amplifiers still need some degree of headroom to work at the resolution level of the ltc2447. for input signals running rail-to-rail, the supply voltage of the lt1368 can be increased in order to provide the extra headroom. the ltc2446/ltc2447 reference have no such limitations they are truly rail-to-rail, and will even operate up to 300mv outside the supply rails. reference terminals may be connected directly to the ground plane or to a reference voltage that is decoupled to the ground plane with a 1 f or larger capacitor without any degradation of performance provided the connection is less than 5cm from the ltc2446/ ltc2447. if the reference terminals are sensing a point more than 5cm to 10cm away from the adc, the reference pins should be decoupled to the ground plane with 1 f capacitors. the reference terminals can also sense a resistive source with a resistance up to 500 ? located close to the ltc2446/ ltc2447, however parasitic capacitance must be kept to a minimum. if the sense point is more than 5cm from the adc, then it should be buffered. the lt1368 is also an outstanding reference buffer. while offsets are not cancelled as in the adc input circuit, the 200mv offset and 2mv/ c drift will not degrade the performance of most sensors. the lt1369 is a quad version of the lt1368, and can serve as the input buffer for an ltc2447 and two reference buffers. ltc2446/ltc2447 27 24467fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701) 5.00 0.10 (2 sides) note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 0.40 0.10 37 1 2 38 bottom viewexposed pad 5.15 0.10 (2 sides) 7.00 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 1203 0.50 bsc 0.200 ref 0.200 ref 0.00 C 0.05 recommended solder pad layout 3.15 0.10 (2 sides) 0.18 0.18 0.23 0.435 0.00 C 0.05 0.75 0.05 0.70 0.05 0.50 bsc 5.20 0.05 (2 sides) 3.15 0.05 (2 sides) 4.10 0.05 (2 sides) 5.50 0.05 (2 sides) 6.10 0.05 (2 sides) 7.50 0.05 (2 sides) 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package ltc2446/ltc2447 28 24467fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/lt 0905 rev a ? printed in usa related parts part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/ c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/ c max drift ltc1799 resistor set sot-23 oscillator single resistor frequency set ltc2053 rail-to-rail instrumentation amplifier 10 v offset with 50nv/ c drift, 2.5 v p-p noise 0.01hz to 10hz ltc2412 2-channel, differential input, 24-bit, no latency ? adc 0.16ppm noise, 2ppm inl, 200 a ltc2415 1-channel, differential input, 24-bit, no latency ? adc 0.23ppm noise, 2ppm inl, 2x speedup ltc2414/ltc2418 4-/8-channel, differential input, 24-bit, no latency ? adc 0.2ppm noise, 2ppm inl, 200 a ltc2430/ltc2431 1-channel, differential input, 20-bit, no latency ? adc 0.56ppm noise, 3ppm inl, 200 a ltc2436-1 2-channel, differential input, 16-bit, no latency ? adc 800nv rms noise, 0.12lbs inl, 0.006lbs offset, 200 a ltc2440 1-channel, differential input, high speed/low noise, 2 v rms noise at 880hz, 200nv rms noise at 6.9hz, 24-bit, no latency ? adc 0.0005% inl, up to 3.5khz output rate ltc2444/ltc2445 8-/16-channel, differential input, high speed/low noise, 2 v rms noise at 1.76khz, 200nv rms noise at 13.8hz, ltc2448/ltc2449 24-bit, no latency ? adc 0.0005% inl, up to 8khz output rate applicatio s i for atio wu uu figure 18. muxed inputs/references enable multiple ratiometric measurements with the same device gnd 5v 5v (18b) full-bridge, current sense 375 ? ch3 + C full-scale output = 60mv to 140mv select for v > 2 ? 140mv at maximum bridge resistance fujikura fpm-120pg (4k to 6k impedance) ch2 v ref23 + v ref23 C gnd 5v 5v omega 44018 linear thermistor composite thermistor (18a) full-bridge, voltage sense (18d) half-bridge, current sense (18c) half-bridge, voltage sense ch0 1 f 1 f 350 ? load cell + C full-scale output = 10mv ch1 v ref01 + v ref45 + ch5 ch4 v ref45 C 2850 ? v ref01 C 1 f lt1790-3 gnd gnd 2850 ? 12.4k t2 t1 100 ? rtd ch7 ch6 v ref67 C 24467 f18 v ref67 + r ilim gnd 500 ? sensor 100 ? at 0 c 247.09 ? at 400 c |
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